This application claims priority to Korean Patent Application No. 2004-92990, filed on Nov. 15, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to display panels, and more particularly, to a source driver with flexible control of a time period for charge share between source lines in a display panel such as for a flat panel display (FPD) device.
2. Description of the Related Art
Flat panel displays (FPDs) include TFT-LCDs (Thin Film Transistor-Liquid Crystal Displays), EL (Electro Luminance) displays, STN-LCDs (Super Twisted Nematic-Liquid Crystal Displays), PDPs (Plasma Display Panels), etc.
Hereinafter, a TFT-LCD, which is the most widely used display, is described. FIG. 1 is a block diagram of a TFT-LCD 100 including a general TFT-LCD panel 110 and peripheral circuits. The TFT-LCD panel 110 includes an upper plate and a lower plate, each including a plurality of electrodes for generating an electric field. A liquid crystal layer is disposed between the upper and lower plates, each having a respective polarization plate for polarizing light.
In the TFT-LCD 100, the brightness of light transmitted through a liquid crystal of each pixel in the panel 110 is controlled by varying a gray voltage applied to each pixel. In order to apply gray voltages to the pixel electrodes, a plurality of switching devices such as TFTs (thin film transistors) are coupled to the pixel electrodes and are disposed on the lower plate of the TFT-LCD panel 110. Each pixel is for emitting light of R (Red), G (Green), or B (Blue) color in an array for displaying images on the LCD panel.
The TFT-LCD 100 includes gate drivers 120 for driving a plurality of gate lines arranged horizontally in the LCD panel 110. The TFT-LCD 100 also includes source drivers 130 for driving a plurality of source lines arranged vertically in the LCD panel 110. The gate drivers 120 and the source drivers 130 are controlled by a controller (not shown). Generally, such a controller is located outside the LCD panel 110. However, the gate drivers 120 and the source drivers 130 may be located on the LCD panel 110 in a COG (Chip On Glass) type TFT-LCD.
FIG. 2 is a block diagram of a conventional source driver 200. Referring to FIG. 2, the conventional source driver 200 includes a driving circuit unit 210 and a channel switching unit 220. The driving circuit unit 210 receives R, G, and B image data of n bits (n=6, 8, 10, or . . . ) and decodes the received image data to generate gray voltages to be output to corresponding channels. The generated gray voltages are output to corresponding source lines through the channel switching unit 220 as image signals.
The image signals output to the corresponding source lines through output channels S1, S2, S3, . . . of the channel switching unit 220 rapidly charge pixels of the LCD panel 110. Liquid crystal molecules of a pixel receiving one of the image signals are rearranged in proportion to the gray voltage of the image signal, thus controlling the brightness of light transmitted by that pixel. The image data is data obtained by processing digital data of a three-color signal (that is, R,G, or B) transmitted from a graphics card, etc. in the controller according to the resolution of the LCD panel 110.
FIG. 3 is a timing diagram of signals such as the channel output signals S1, S2, S3, . . . and a load control signal LOAD during operation of the source driver of FIG. 2. Referring to FIG. 3, the driving circuit unit 210 latches image data under the control of a data input/output control signal DIO and decodes the latched data. That is, after the data input/output control signal DIO transits from a logic low state to a logic high state, the driving circuit unit 210 latches and decodes image data. At this time, a system clock signal CLK is used as a reference synchronization signal.
A period during which the data input/output control signal DIO is in the logic low state after being in the logic high state may be included in a blanking period during which a load control signal LOAD may be activated to the logic high state. If the load control signal LOAD is thus activated, the channel switching unit 220 causes the output channels S1, S2, S3, . . . to enter a high impedance state (Hi-Z) and an interchannel charge-share state, thereby preventing the gray voltages generated by the driving circuit unit 210 from being transferred to the source lines. That is, the channel switching unit 220 transfers gray voltages (Y(n−1), Y(n), . . . ) generated by the driving circuit unit 210 to the source lines through the output channels S1, S2, S3, . . . only while the load control signal LOAD is deactivated to the logic low state.
In order to cause the output channels S1, S2, S3, . . . to enter the Hi-z state and the charge-share state for precharging the pixels, the load control signal LOAD is activated to the logic high state during each horizontal scan period, as shown in FIG. 3. However, conventionally, the output channels S1, S2, S3, . . . are in such a Hi-z state during the entire activated period of the load control signal LOAD, which may not be suitable for large, high-resolution LCD panels. For example, since a horizontal scan period is short for high resolution and accordingly the number of clock cycles during a blanking period, etc. is limited, a timing margin is deteriorated.
To solve this problem, the activated period of the load control signal LOAD may be reduced. However, such reduction has limitations since performing a precharge operation within such a short time period may be difficult.